Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
It should be understood that a “global placement” places components in a netlist without assigning circuit resources. An initial global placement may not result in a “legal” or “valid” placement, as the demand for resources in a region may exceed the supply of such resources in such region, namely an overlap. Conventionally, an “analytical placement” was used to optimize wirelength and spread resources to reduce such overlap. Thus, a design may be iteratively globally and analytically placed to obtain a “legal” design. The process of obtaining a design without overlap is sometimes referred to as “legalization.” A “detailed placement” or “full placement” assigns each component in the netlist to specific resources for an implementation and may try to improve a cost function. A “detailed placement” or “full placement” may start with a legalized placement. However, more commonly, a detailed placement includes a legalizer, and thus a detailed placement may take a result from a global placement having overlaps and produce an optimized overlap-free result. The terms “global placement,” “analytical placement,” and “detailed” or “full placement” are known in the art.
When placing components of a circuit design for generating a netlist to be used to instantiate a design in an FPGA, it is possible that certain components will be placed in a same localized region of FPGA fabric. Thus more than one component may be placed in a same localized region. However, the control sets for components placed in a same localized region in some instances are different. Heretofore, components placed in a same localized region, such as a slice in FPGA fabric, had to have the same control set, and thus components in a same localized region with conflicting control sets had to be re-placed to resolve the conflict. It should be understood that when there is a relatively high amount of control set contention, producing a valid or “legal” solution using conventional means may involve deviating too much from the original solution obtained from a global placement. Such a deviation may have negative impact on various metrics, such as for example timing, power, and wirelength, among others, that were attempted to be optimized as part of a global placement.
Accordingly, it would be desirable and useful to provide means to resolve such limitation without having to re-place a component with a conflicting control set in order to increase packing density.